Technique for generating hash-tuple independent of precedence order of applied rules

ABSTRACT

Techniques have been developed to facilitate evaluation of match and hash rule entries in ways that allow an implementation to decouple (i) the order in which match rules are applied to a first subset of packet header fields from (ii) the ordering of a second subset of packet header fields over which a non-commutative hash is computed. In short, the set and ordering of fields evaluated in accordance with a precedence order of rules need not correspond to the set or ordering of fields over which a hash is computed in a communications controller.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application is related to commonly owned U.S. application Ser. No. 12/404,140, filed 13 Mar. 2009, entitled “Programmable Hash-Tuple Generation with Parallel Rule Implementation Independence” and naming Xu and Kramer as inventors.

BACKGROUND

1. Field

This disclosure relates generally to data processing systems, and more specifically, to computationally efficient mechanisms for calculating a hash over information that is evaluated, at least partially, in coordination with match rules.

2. Related Art

Modern packet-routed communications involve the use of numerous specialized hardware and software techniques to parse packet headers and to direct flows of related packet information based on the header fields parsed. In some cases, it can be desirable to calculate a hash over at least a portion of the information parsed from individual packet headers so as to deterministically distribute computations or flows in a way that maintains locality with respect to some aspect of the hashed over information. For example, hashes are commonly used in packet routing implementations that seek to achieve load balance by distributing packets over a range of processing queues, targets or other resources.

Typically, packet routing implementations parse field information from headers and evaluate field contents (e.g., source addresses, destination addresses, protocol, etc.) in order to make routing and filtration decisions. In programmable implementations, these evaluations may be coded as match rules. For example, a destination IP address may be masked (to mask away all but a network/sub-network portion of the address) and matched against one or more network/sub-network address codings to determine whether corresponding information should be routed onward and, if so, in what manner.

In some cases, it may be desirable to include in a hash computation certain field contents that are evaluated by match rules. Some implementations of hash techniques and, in particular, some implementations that exhibit good avalanche and diffusion properties, are non-commutative. As a result, different orderings of field values may produce different hash results. In some applications, hash results resulting from different field orderings are all equally valid and useful. However, in some applications or implementations, it may be desirable to ensure that hash results are deterministically computed over some particular ordered set of fields. In general, a set and ordering of fields desirable for purposes of hash computation need not correspond to the set and order of fields evaluated in accord with match rules. Rather, evaluation order will typically correspond to a pertinent decision tree of field match predicates. On the other hand, a desirable ordering for hash computations may trace to factors such as utility the resultant hash at a higher-level protocol, or may trace to design requirements for determinism in the face of rule set revisions and/or varying levels of concurrency across a range of product implementations. In any case, desirable precedence orders for match rule evaluation do not typically (or necessarily) correspond to a desirable ordering of field values over which a hash is computed.

Accordingly, computationally efficient techniques are desired that decouple the ordering of match rule evaluations from that employed in hash computations.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

FIG. 1 is a block diagram illustrating a communications controller configuration in which a core-affinity preserving distribution of packet traffic is achieved using techniques in accordance with some embodiments of the present invention.

FIG. 2 is a block diagram of a multi-stage, filtered hash chain configured for multi-cycle evaluation of a hash rule set in accordance with some embodiments of the present invention.

FIG. 3 depicts flows in accordance with a first of four (4) cycles through an illustrative 4-stage filtered hash chain in accordance with some embodiments of the present invention.

FIG. 4 illustrates flows in accordance with a second of four (4) cycles through an illustrative 4-stage filtered hash chain in accordance with some embodiments of the present invention.

FIG. 5 illustrates flows in accordance with a final one of four (4) cycles and through an illustrative 4-stage filtered hash chain together with a final hash through in accordance with some embodiments of the present invention.

FIGS. 6 and 7 illustrate, in accordance with some embodiments of the present invention, corresponding in-memory footprints for rule sequences that produce a consistent hash despite dissimilar allocations of individual hash rules to memory banks.

The use of the same reference symbols in different drawings indicates similar or identical items.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

Techniques have been developed to facilitate evaluation of match and hash rule entries in ways that allow an implementation to decouple (i) the order in which match rules are applied to a first subset of packet header fields from (ii) the ordering of a second subset of packet header fields over which a non-commutative hash is computed. In short, the set and ordering of fields evaluated in accordance with a precedence order of rules need not correspond to the set or ordering of fields over which a hash is computed in a communications controller.

In some embodiments, protocol traffic (including corresponding hashes computed at a communications controller) may be distributed amongst processing elements (e.g., processor cores of a system on a chip) to which higher-level protocol processing tasks are assigned. In such embodiments, the decoupling of hash ordering from a precedence order of match rules facilitates selection of a particular hash ordering that is consistent with needs or conventions employed in a corresponding higher-level protocol processing task.

In some embodiments, such a decoupling can facilitate selection on a packet-type basis of an appropriate ordered set of fields over which a corresponding hash is to be computed. For example, in some embodiments, hashes computed over an ordered set of header fields, e.g., the ordered set {IPSA, IPDA, PROT, SP, DP}, selected at the communications controller, e.g., based on match rules that identify IP protocol traffic destined for TCP port 80, may be supplied to a processing element that services hypertext transfer protocol (HTTP) traffic for use as a hash key that selects amongst server and/or session contexts being serviced at the processing element. In this way, optional hardware acceleration of hash computations may be employed and, in some embodiments, computation or recomputation of appropriate hash at the higher-level protocol implementation can be avoided.

For concreteness of description, we focus on certain illustrative implementations of a communications controller with acceleration logic that facilitates concurrent evaluation of match rules and employs a filtered hash chain coupled thereto that facilitates hash result determinism irrespective of any particular allocation of match rules to evaluation units. Of course, embodiments of the present invention are not limited to the illustrated communications controller, to any particular hash generator or non-commutative hash. Also for concreteness, system on a chip (SoC) embodiments are described in which individual processor cores constitute processing elements suitable for (amongst other things) higher-level protocol tasks and are integrated on chip with a communication controller. However, based on the description herein persons of ordinary skill in the art will appreciate applications of the invented techniques to other functional blocks, systems and/or integrated circuits. Indeed, some communication controller embodiments in accordance with the present invention need not be integrated with processing elements suitable for higher-level protocol tasks.

Techniques described herein have broad applicability to a wide range of information processing architectures, device implementations and types of protocol traffic and underlying communications technologies, but will nonetheless be understood and appreciated by persons of ordinary skill in the art in the illustrated context of Ethernet-type communication controllers, routing techniques and protocol traffic typical of applications and services commonly associated with internet communications. Accordingly, in view of the foregoing and without limitation on the range of information processing architectures, device implementations, types of protocol traffic and communications technologies that may be employed in embodiments of the present invention, we describe certain illustrative embodiments.

Systems Realizations, Generally

FIG. 1 is a block diagram illustrating a computational system 100 in which a communications controller 110 facilitates a core-affinity preserving distribution of packet traffic using hash generation techniques in accordance with some embodiments of the present invention. In the illustrated configuration, communications controller 110 is coupled between a physical layer (PHY) block 120 of a communications architecture and the processor(s) 101 and memory 102 of computational system 100.

FIG. 1 illustrates a simple illustrative configuration in which a bus-type interconnect 104 couples processors 101, communications controller 110 and addressable storage presented as memory 102. Data transfers between communications controller 110 and memory 102 are facilitated using DMA interface 112 and bus interface unit 111. Nonetheless, persons of ordinary skill in the art will appreciate that any of a variety of interconnect topologies, memory hierarchies and I/O interfaces may be employed in other embodiments. In this regard, the illustration of FIG. 1 is not meant to be limiting but to rather serve as a useful descriptive context in which certain inventive concepts will be understood. In other embodiments, modern front-side multi-path interconnect fabrics that support concurrent non-conflicting transactions and high data rates may be employed together with multiple tiers of interconnects including specialized I/O interconnects and suitable bridging and coherence technologies. Based on the description herein, persons of ordinary skill in the art will appreciate suitable implementations in, and adaptations for, more or less complex computational systems.

In general, embodiments of communications controller 110 may implement any of a variety of channel access mechanisms, information frames and headers. Nonetheless, for concreteness of description, illustrations herein tend to focus on traffic and terminology typical of Ethernet-type data link layer implementations. Accordingly, for purposes of illustration and in accord with OSI model nomenclature, the embodiment of FIG. 1 includes an Ethernet media access control (MAC) block 113 that interfaces with PHY block 120. In general, suitable MAC and PHY implementations are well known in the art and Ethernet MAC 113 and PHY 120 are of any suitable design.

As is typical, Ethernet MAC 113 operates on information frames sometimes referred to as packets, which typically encode both header information and a body or data portion. For example, information frames received at a block such as Ethernet MAC 113 and typically encode source and destination MAC-level physical address fields, e.g., MAC_SA and MAC_DA fields, together with an EtherType field that identifies the type (e.g., Internet protocol version 4 [IPv4], address resolution protocol [ARP], Novell IPX, IPv6, etc.) of data conveyed. Encapsulated within the MAC-level body of a received information frame (or packet) are further headers and associated data portions. For example, internet protocol traffic includes its own headers which encode, amongst other fields, IP-level source and destination addresses, e.g., as IPSA and IPDA fields and a protocol, e.g., as a PROT field, that identifies the associated IP-level data portion as Internet message control protocol [ICMP] data, transmission control protocol [TCP] data, user datagram protocol [UDP] data, etc.). Encapsulated data portions can be characterized by further headers and data portions. For example, further encapsulated within TCP protocol data (sometimes referred to as a TCP segment) are additional headers and associated data. Such TCP segments conventionally encode (amongst other things) source and destination ports, e.g., as SP and DP fields, together with an associated data portion.

Persons of ordinary skill in the art will appreciate that, in general, received information frames include, typically at successive levels of encapsulation, numerous header field values that may be parsed from respective headers and thereby inform packet routing, decisioning and processing at data link and further layers in an information processing architecture. In particular, for purposes of illustrating some embodiments, it will be apparent that, for an IPv4 packet that conveys TCP traffic, an illustrative subset of such fields includes MAC_SA, MAC_DA, EtherType, IPSA, IPDA, PROT, SP and DP fields parsable from respective MAC-, IP- and TCP-level headers. Field lengths, offsets and type indications for successively encapsulated header and data are typically the subject of agreed or de facto standards and, in any case, techniques for reliably parsing field values from such headers and associated data are well understood in the art. Thus, for clarity of description, header fields and operations thereon (such as match rule evaluations and hash computations) are discussed in the material that follows without particular regard to the levels in successively encapsulated information codings at which any given header field appears.

In some embodiments, a substantial portion of a computational system such as that illustrated in FIG. 1 is implemented as a system on a chip (SoC) and embodied as a single integrated circuit chip 199. In such configurations, some storage of a memory hierarchy (e.g., a portion of a hierarchy illustrated collectively as memory 102) and/or a subset of blocks such as PHY 120 may be implemented off-chip, while the substantial entirety of otherwise illustrated blocks may be packaged as an SoC. In such configurations, interface 114 may implement a SerDes-type interface with an off-chip PHY 120 and memory controllers (not specifically shown) may provide an interface between off chip portions of memory 102 and one or more levels of on-chip cache. In other embodiments and more generally, portions of computational system 100 may be implemented in or as separate integrated circuits in accord with design, packaging or other requirements.

Focusing now on logical link control (LLC) block 115, various protocol multiplexing and flow mechanisms typical of an OSI model logical link sub-layer implementation are provided. LLC block 115 parses packet headers to extract certain fields (e.g., source addresses, destination addresses, protocols, ports, checksums, etc.) coded therein to facilitate multiplexing of protocols (e.g., IP, IPX, etc.), flow control, as well as detection and control of certain dropped packet errors (e.g., through retransmission). Suitable LLC sub-layer implementations are well known in the art and LLC block 115 includes any of a variety of such implementations. However, in addition, in some embodiments of the present invention, specialized hardware accelleration logic is provided to compute hashes over selected ones of the parsed packet header fields.

Although neither necessary or essential, in some embodiments in accordance with the present invention, selection of a particular subset of fields over which to compute a hash may be accomplished using programmably-defined match rules that evaluate header information in accordance with a decision tree and where certain ones of the match rules further direct a hash generator to include the corresponding field value in a hash computation. More generally, decision logic need not be programmable (or reprogrammable) and the specification of packet header field evaluations and the subset of field values to be included in a hash need not be accomplished using a unified rule framework.

In view of the above, and without limitation, in the illustration of FIG. 1, accelleration logic 130 includes a plurality of logic blocks 131 that seek to apply respective hash-indicating match rules to packet header fields and thereby compute a composite hash over selected field values so identified. In general, the subset of fields over which a hash is to be computed may vary depending on protocol and/or service. For example, for transmission control protocol (TCP) traffic with a destination port for hypertext transfer protocol (HTTP), a desirable hash may be:

-   -   hash (IPSA, IPDA, PROT, SP, DP)         where IPSA and IPDA are the IP source and destination address         field values, PROT is the protocol field value, and SP and DP         are the source and destination port field values, all parsed         from the packet header. In contrast, for internet control         message protocol (ICMP) traffic, a hash over a different set of         field values, e.g.,     -   hash (IPSA, IPDA)         may be desirable. For other types of protocol traffic, hashes         over still different sets of field values, e.g.,     -   hash (MAC_DA, MAC_SA)

may be desirable.

In the illustration of FIG. 1, accelleration logic 130 and associated rule codings in rule store 132 implement field value match criteria, predicate testing and hash computations. To achieve hardware accelleration, multiple instances of logic blocks 131 are provided and individual rule elements that code appropriate matches, masks, predicates and hashes are distributed over logic blocks 131 for evaluation (in parallel) against respective parsed field values. To support high data rates, in some embodiments, a plurality of independently accessible sub-portions of rule store 132 are provided, e.g., as static memory (SRAM) banks individually associated with corresponding ones of the logic blocks 131 and coding therein a respective fractional portion of the overall rule set. Contributions from individual ones of the logic blocks 131 are combined (133) as a hash value for use in connection with the associated packet.

Thus, building on the hash examples above, accelleration logic 130 can be used (given appropriate rules coded in rule store 132) to calculate hashes in a way that allows LLC block 115 to distribute (139) packets amongst a plurality of in-memory queues 1051, 1052 . . . 1053 in accord with protocol-specific core-affinity preserving workload distributions. For example, in the case of HTTP packet traffic, it can be desirable to distribute processing load across multiple processors 1011, 1012 . . . 1013 while still ensuring that all packets bearing the same source and destination addresses and ports be routed to a same one of processors (e.g., to processor 1012 via queue 1052). Such a criterion may be achieved by using a hash over source and destination address and ports and by partioning the resultant hash space into portions that correspond to individual processors.

In the illustration of FIG. 1, DMA transfers 197 of at least some packet data target an appropriate one of the in-memory queues 1051, 1052 . . . 1053 which is selected based on a hash computed over a rule-specified portion of the associated packet header fields. Individual processors access (198) information in a respective one of the in-memory queues (e.g., processor 1012 from queue 1052). Thus, core-affinity workload distributions are achieved using hash computations performed by accelleration logic 130 and the evaluation of hash rule elements (in parallel) using the multiplicity logic blocks 131 facilitates high packet rates necessary or desirable to feed higher-layer protocol computations (e.g., network-, transport-, session-, presentation- and/or application-layer protocol computations) performed at processors 101 or elsewhere.

In some embodiments, I/O virtualization techniques may be supported, and fractioning of packet traffic (e.g., based on a multiplicity of virtual communications controllers and associated IP addresses or any other suitable criterion) may also occur. In such cases, additional mappings, e.g., between I/O and host domains and other virtualization-oriented techniques may be supported within communications controller 110 or elsewhere. Based on the description herein, persons of ordinary skill in the art will appreciate suitable virtualization-oriented extensions to communications controller 110; nonetheless, for clarity of descriptive context though without limitation, illustrations and examples herein tend to omit further reference to I/O virtualization.

Finally, in some embodiments, communications controller 110 may include support for a different set of layers (and/or sub-layers) of an implemented protocol stack (or stacks). In this regard, illustrations and examples of allocations of network-, transport-, session-, presentation- and/or application-layer protocol computations to any particular component (e.g., to processors 101) are design- and/or implementation-dependent choices. Based on the description herein persons of ordinary skill in the art will appreciate other design and/or implementations suitable for other allocations of protocol layer/sub-layer computations (including allocations that support additional layers/sub-layers of the protocol computations within communications controller 110 itself, or using some other component(s)). Again, for clarity of descriptive context though without limitation, illustrations and examples herein tend to omit alternative allocations of protocol layer/sub-layer computations.

Match/Hash Rule Set Examples

Much of the description herein will be understood in the context of an evaluation (by communications controller 110) of header fields parsed from a received information frame where the evaluation is consistent with the decision tree and selections of header fields for inclusion in a hash as specified in the following pseudo-code.

If IP   If PROT = ICMP     HASH{IPSA,IPDA} Elseif IP & TCP   If TCP_dest_port = 80     HASH{IPSA,IPDA,PROT,SP,DP}   Elseif TCP_dest_port = 21     HASH{IPSA,IPDA,PROT} Else   HASH {MAC_DA,MAC_SA}

In accord with the forgoing, desired operation of communications controller 110 and any accelleration logic 130 thereof, provides that different hashes are to be computed for:

-   -   an ICMP packet;     -   a packet conveying a TCP segment that codes HTTP traffic;     -   a packet conveying a TCP segment that codes FTP traffic; or     -   some non-IP packet.

For at least some encodings of the illustrated pseudo-code as a programmably-defined rule set suitable for evaluation of packet headers (e.g., as match rule entries coded in rule store 132 for concurrent evaluation against parsed header fields using logic blocks 131 of accelleration logic 130), individual rule entries encode masking operations, predicate tests based on specific header field values, and optional selection of selected corresponding field values for inclusion in hash. Thus, in some rule encodings, a set of non-hashed and hashed rule entries such as follows:

If ((MASK&MATCH {EtherType} = IP) &&   (MASK&MATCH {PROT} = ICMP))    MASK MATCH&HASH {IPSA}    MASK MATCH&HASH {IPDA} Elseif (MASK&MATCH {PROT} = TCP)    If (MASK&MATCH {DP} = 80)     MASK MATCH&HASH {IPSA}     MASK MATCH&HASH {IPDA}     MASK MATCH&HASH {PROT}     MASK MATCH&HASH {SP}     MASK MATCH&HASH {DP}    Elseif (MASK&MATCH {DP} = 21)     MASK MATCH&HASH {IPSA}     MASK MATCH&HASH {IPDA}     MASK MATCH&HASH {PROT} Else    MASK MATCH&HASH {MAC DA}    MASK MATCH&HASH {MAC SA} is used to define behavior of a hash generator. Note that by decoupling the order and subset of field value over which a hash is computed from the order in which match rules evaluate header fields to implement an appropriate decision tree, the illustrated set of non-hashed and hashed rule entries allows both an efficient evaluation and coding of decision logic and arbitrary orders (and independently defined) field orders for the selected hash computation.

In addition, by allowing selection of an appropriate subset and ordering of field values for inclusion in the hash (e.g., based on the type of protocol traffic conveyed by a given information frame), the techniques described herein facilitate use of hashes computed at a communications controller in furtherance of higher-level protocol processing. For example, referring to FIG. 1, a hash computed at communications controller 110 may be conveyed with corresponding content from the received information frame to a particular processing element 101, whereupon the conveyed hash may be used to retrieve a processing context pertinent to evaluation of the corresponding content. In particular, relative to HTTP protocol traffic, a hash over a suitably selected ordered subset of field values may be used to retrieve an appropriate a web server context. In other cases, a suitably selected ordered subset of field values may be hashed and used as index for lookup in a cached (L2 or L3) table for packet forwarding. Likewise, for session initiation protocol (SIP) traffic, a different ordered subset of field values may be hashed and used as index for lookup in a SIP routing table. In some implementations, a suitably selected subset and ordering of field values that code addressing information for media transfer protocol traffic may be used in a hash computed at the communications controller but also usable at a processing element to index media content for a particular source.

Filtered Hash Chain Implementation

FIG. 2 is a block diagram illustrating a hash generator 250 that includes a multi-stage, filtered hash chain 251 configured for use in accordance with some embodiments of the present invention as part of accelleration logic 130. In the illustrated configuration, match rules (including hashed and non-hashed entries) are distributed across a plurality of N SRAM banks 2321, 2322 . . . 2323 for a multiple (M) cycle evaluation of a rule set coded therein. For simplicity and in accord with the described rule coding, match rules that are indicated as contributing to a hash are sometimes referred to (herein) as hash rules, whereas those not so indicated are sometimes referred to as non-hash rules. As before, individual rule entries code appropriate matches, masks, predicates and/or hashes and are distributed over the memory banks to allow evaluation (in parallel) against fields (e.g., header parse results 291) parsed from a packet header against which the hash rule set is to be applied. In this way, N sub-portions (2331, 2332 . . . 2333) of evaluation logic 233 operate to individually (and in parallel) apply a respective indexed rule entry retrieved from a corresponding SRAM bank to header parse results 291. For example, in a first cycle, a first set of indexed rule entries are applied from the respective banks. In a second cycle, a second set of indexed rule entries are applied. In general, successive cycles apply successive sets of indexed rule entries until a total of up to M*N rule entries are applied in M cycles.

Note that, in some embodiments of the present invention, use of a filtered hash chain such as illustrated in FIG. 2 allows concurrent N-wide evaluation of plural rule entries and hash contributions, while still allowing hash contributions to be selectively included in a hash result based on results of a down-chain match evaluation. Furthermore, in some embodiments consistent with the illustration, multi-cycle operation of the filtered hash chain allows sequential evaluation of large rule sets that includes more rules than may otherwise be evaluated in a single cycle give practical constraints on extent of the hash chain (e.g., based on gate delays through the hash chain). Nonetheless, neither a filtered hash chain nor its multi-cycle use are necessary or essential for all embodiments of the present invention. Indeed, in some embodiments, an alternative implementation of hash generator 250 may simply evaluate hash rules sequentially without use of the illustrated filtered hash chain or alternatively may employ other techniques for coordinating concurrently evaluated match rules and/or hash contributions. Therefore, in view of the above and without limitation, we refer again to the illustration of FIG. 2.

In the illustrated configuration, logic that computes the hash is partitioned into two major portions: a filtered hash chain 251 portion and a hash final (HF) portion 252. The filtered hash chain 251 portion selectively introduces hash intermediate (HI) contributions computed in stages 281, 282 . . . 283 based on respective header parse results. In particular, potential hash contributions computed at a given stage (e.g., at HI blocks 241, 242 . . . 244) are selectively introduced into an accumulated hash based on hash rule entry evaluations performed at each stage. In the illustrated configuration, during each cycle, the accumulated hash propagates laterally (downstream) through filtered hash chain 251, accumulating HI contributions (if any) based on then-indexed hash rule entries applied to parsed header fields of a current packet. In anticipation of possible inclusion, each stage XORs (e.g., at logic 271, 272 . . . 274) the applicable parsed header field value (i.e., for the field identified by the currently indexed hash rule entry) with the net accumulated hash value propagated from its upstream neighbor and applies the HI computation to that combined value. Multiple cycles through filtered hash chain 251 are used to selectively introduce HI contributions based on subsequently-indexed hash rule entries applied to parsed header fields of a current packet. Finally, the hash calculation concludes with a calculation (at hash final (HF) portion 252) over accumulated HI contributions introduced in preceding stages and cycles.

Selective introductions of HI contributions depend on the results of a rule entry application at a given stage (e.g., initial stage 281, next stage 282 . . . final stage 283). In general, such results control respective MUX selections (e.g., signals 211, 212) that, for a given stage of filtered hash chain 251:

-   -   (i) reset the propagating hash value (using hash reset value 292         supplied from evaluation logic 233),     -   (ii) introduce a current stage hash contribution into the         accumulated hash value and propagate same downstream, or     -   (iii) bypass the current stage HI contribution and instead         couple through the prior-stage accumulated hash value.

Hash contributions for possible introduction into the propagating hash value are computed at any given stage based on pertinent field values parsed from the current packet header. For example, in the illustrated embodiment, focusing illustratively on stage 282, a hash value propagating from upstream filtration multiplexer (MUX) 261 is XORed (at 272) with a parsed header field result 291 value corresponding to the hash rule entry applied (in the current cycle) at evaluation logic sub-portion 233B. Hash intermediate (HI) logic 242 computes a hash contribution over the XORed value and supplies the resulting accumulation of prior stage/cycle HI contributions as input 293 to filtration MUX 262.

Depending on the results of the rule entry evaluation (at 233B), MUX select signal 212 directs filtration MUX 262 to select an appropriate one of inputs 293, 294 and 295. For example, if the rule entry applied at evaluation logic 233B is a hash-type rule entry with a matched field value, then select signal 212 directs filtration MUX 262 to propagate the output of HI logic 242 (i.e., the accumulated hash with current stage HI contribution presented at input 294) downstream. If the rule entry applied at evaluation logic 233B is an unmatched (or failed) compound rule entry (e.g., a rule entry that codes an AND conjunction of matches tested by one or more prior stage rule entries), then select signal 212 directs filtration MUX 262 to propagate downstream the hash reset value 292 presented at input 293. If the rule entry applied at evaluation logic 233B is a non-hash type rule entry (e.g., a rule entry that codes a mask setup, predicate evaluation, etc.), then select signal 212 directs filtration MUX 262 to bypass the current stage contribution and simply pass the prior-stage accumulated hash value (e.g., that conveyed via bypass path 277 and presented at input 295) downstream.

After a final stage 283 of filtered hash chain 251, a second-level filtration MUX 263 selects (using select signal 214) a furthest downstream output (e.g., one of filtered hash chain 251 outputs presented at 296, 297 . . . 298) for which a hash-type rule evaluation matched. As before, if evaluation logic (here, evaluation logic 233C) indicates an unmatched (or failed) compound rule entry then select signal 214 directs second-level filtration MUX 263 to propagate hash reset value 292 presented at input 299.

Assuming that a second-level filtration MUX 263 input is selected, it is propagated to latch 256 where, if an additional cycle through filtered hash chain 251 remains, it is available as the prior cycle output 258 for propagation downstream as the prior stage/cycle accumulated hash. In general, successive cycles through filtered hash chain 251 incorporate the accumulated hash value output in the prior cycle. In those cases, where matching hash rules result in a prior cycle contribution to the accumulated hash, the value from the next prior cycle (or seed 259, if applicable) may be recycled using an additional input (not specifically shown) to second-level filtration MUX 263 or simply by retaining the prior cycle output value in latch 256. Note that seed 259 may be introduced for use in a first cycle via second-level filtration MUX 263.

If the accumulated hash value stored in latch 256 is the output of a final cycle through filtered hash chain 251, then the hash calculation concludes with a calculation (at hash final (HF) portion 252) over accumulated HI contributions introduced in preceding stages and cycles. Hash result 203 is latched (at 257) and supplied for use in any appropriate way, including e.g., for use in the previously illustrated core-affinity routing technique.

Partitioned Hash Function Example

In the illustration of FIG. 2, logic that computes a hash over a hash-rule-specified set (and ordering) of packet header field values is partitioned into hash-intermediate and hash-final portions. In general, any of a variety of hash functions may be suitably partitioned into similar portions and used in embodiments such as described herein. Accordingly, the exemplary partition of hash-intermediate and hash-final portions that follow are for purposes of illustration and should not be interpreted as limiting the range of suitable hash functions and partitions thereof that may be employed in embodiments of the present invention. Rather, based on the described partition of hash-intermediate and hash-final portions, persons of ordinary skill in the art will appreciate other suitable overall hash functions and partitions that may be appropriate or desirable in other embodiments or situations.

In view of the foregoing and without limitation, one suitable hash function is a concrete implementation (e.g., in logic) of a mathematical function ORD(i,j). The function ORD(i,j) takes two parameters (i and j) that specify shift amounts. The function ORD(i,j) operates on the implied operand that represents internal state of the hash s. An evaluation of the function ORD(i,j) implemented in silicon operates as a logic cascade and sets the new internal state as follows: s′=s^(s<<i)^((s<<j|s<<(i+j))) where negative values for i and j designate a right-shift rather than the otherwise apparent left-shift. In general, the ORD function has been selected after noting that add functions can provide good avalanche/diffusion properties, but may be too slow for some silicon implementations (such as of filtered hash chain 251 described herein) since around four or more cascaded adds could be required each cycle. Persons of ordinary skill in the art may recognize that the ORD( ) function is reminiscent of certain half-adder equations, but with a few changes to increase diffusion. Persons of ordinary skill in the art may recognize that an ORD( ) based hash function is non-commutative. Other non-commutative hash functions will be apparent to persons of ordinary skill in the art based on the description herein and any applicable design factors.

In any case, a 32-bit ORD( ) based hash function is used in some embodiments of the present invention, e.g., to hash IPv6 source and destination address values parsed from packet headers and thereby maintain core-affinity in a communications controller design such as previously illustrated. For purposes of illustration, hash-intermediate (HI) and hash-final (HF) portions of the 32-bit ORD( ) based hash function will be understood as follows. HI logic instances, e.g., HI logic 241, 242 . . . 244, are silicon logic implementations of the following:

hash-intermediate( ) {  s = ORD(1,6);  s = ORD(−14,−3);  s = rotate(s,11); } Correspondingly (and again relative to FIG. 2 and in accord with some embodiments of the present invention), HF logic 252 is a silicon logic implementation of the following:

hash-final( ) {  hash-intermediate( );  hash-intermediate( );  hash-intermediate( ); }

Notwithstanding the foregoing detail, particular hash functions and particular partitions thereof into hash-intermediate and hash-final portions are purely illustrative and should not be interpreted as limiting the range of suitable hash functions and/or partitions thereof that may be employed in embodiments of the present invention.

Filtered Hash Chain, Multi-Cycle Example

Building on the forgoing description, FIG. 3 depicts flows through an illustrative 4-stage filtered hash chain in accordance with some embodiments of the present invention. In particular, FIG. 3 provides a working example for a first of four (4) cycles through a 4-stage filtered hash chain implementation patterned on that described above with reference to FIG. 2. An illustrative set of hash rule entries are distributed across four SRAM banks that together constitute a rule set and which cause evaluation logic 333 to perform packet header field match and hash operations. Those rule entries include two hash rule entries HR0 and HR1 that appear in a first indexed position 332 within respective banks and six additional hash rule entries (HR2, HR3, HR4, HR5, HR6, and HR7) that appear in respective subsequent indexed positions within respective banks. Non-hash rules NR are also illustrated and appear in respective indexed positions within respective banks.

More particularly, FIG. 3 illustrates first cycle 301 flows through a 4-stage embodiment of the previously described filtered hash chain based on an illustrated rule subsequence {NR, HR0, HR1, NR} distributed across the first indexed position 332A of the respective banks. Because the first indexed position of the bank associated with the initial stage of the illustrated hash chain (recall stage 281, FIG. 2) codes a non-hash rule, hash-intermediate computations (if any) by HI logic 341 are not propagated downstream. Rather, an input sourced from a bypass path (here coding the initial hash seed) is selected by filtration MUX 361 and supplied for downstream use in the next stage.

The first indexed position of the bank associated with the second stage of the illustrated hash chain codes a hash rule (i.e., hash rule HR0) that, for purposes of illustration, we assume matches the corresponding field value parsed from the packet header. Accordingly, that matched field value is combined with the output of the prior stage using XOR 372 and supplied to HI logic 342 for use in a hash-intermediate computation, the results of which are passed through filtration MUX 362 based on a select signal appropriate the matched hash rule. Contents of the first indexed position of the bank associated with the third stage also code a hash rule (i.e., hash rule HR1) that, again for purposes of illustration, we assume matches the corresponding field value parsed from the packet header. Accordingly, that matched field value is combined with the output of the prior stage using XOR 373 and supplied to HI logic 343 for use in a hash-intermediate computation, the results of which are passed through filtration MUX 363 based on a select signal appropriate to the matched hash rule.

Because the first indexed position of the bank associated with the fourth stage codes a non-hash rule, the last hash rule match (during this cycle) is in the third stage and accordingly a select signal directs second-level filtration MUX 364 to couple through the corresponding input and supply the accumulated hash value as output 358 for using in a next cycle 302 through the filtered hash chain. That next cycle 302 is illustrated in greater detail in FIG. 4.

Building on the foregoing, FIG. 4 illustrates second cycle 302 flows through the 4-stage embodiment of the previously described filtered hash chain based on an illustrated rule subsequence {HR2, NR, NR, HR3} distributed across the second indexed position 432 of the respective banks. The second indexed position of the bank associated with the initial stage of the illustrated hash chain codes a hash rule (i.e., hash rule HR2) that, for purposes of illustration, we assume matches the corresponding field value parsed from the packet header. Accordingly, that matched field value is combined with output 358 of prior cycle 301 using XOR 371 and is supplied to HI logic 341 for use in a hash-intermediate computation, the results of which are passed through filtration MUX 361 based on a select signal appropriate to the matched hash rule. Because the second indexed position of the bank associated with the second stage of the illustrated hash chain codes a non-hash rule, hash-intermediate computations (if any) by HI logic 342 are not propagated downstream. Rather, an input sourced from bypass path 377 (here coding the hash accumulated through the prior stage) is selected by filtration MUX 362 and supplied for downstream use in the next stage.

Again in the third stage of the illustrated hash chain, the corresponding second indexed position in the associated bank codes a non-hash rule and, accordingly, hash-intermediate computations (if any) by HI logic 343 are not propagated downstream. Rather, an input sourced from bypass path 378 is selected by filtration MUX 363 and is supplied for possible downstream use in the fourth stage. Since the second indexed position of the bank associated with the fourth stage of the illustrated hash chain codes a hash rule (i.e., hash rule HR3) and since, for purposes of illustration, we again assume that the hash rule matches the corresponding field value parsed from the packet header, the matched field value is combined with the output of prior stage filtration MUX 363 using XOR 374 and supplied to HI logic 344 for use in a hash-intermediate computation, the results of which are passed through second-level filtration MUX 364 based on a signal selective for the accumulated hash output of the stage (here the fourth stage) containing the last hash rule match during this second cycle 302. Second-level filtration MUX 364 couples through the corresponding input and supplies it as output 458 for using in a next cycle 303 through the filtered hash chain.

Skipping ahead, FIG. 5 illustrates flows during a fourth and final cycle 304 through the 4-stage embodiment of the previously described filtered hash chain based on an illustrated rule subsequence {HR6, NR, HR7, NR} distributed across the fourth indexed position 532 of the respective banks. The fourth indexed position of the bank associated with the initial stage of the illustrated hash chain codes a hash rule (i.e., hash rule HR6) that, for purposes of illustration, we assume matches the corresponding field value parsed from the packet header. Accordingly, that matched field value is combined with output 558 of prior cycle 303 using XOR 371 and supplied to HI logic 341 for use in a hash-intermediate computation, the results of which are passed through filtration MUX 361 based on a select signal appropriate to the matched hash rule. Because the fourth indexed position of the bank associated with the second stage of the illustrated hash chain codes a non-hash rule, hash-intermediate computations (if any) by HI logic 342 are not propagated downstream. Rather, an input sourced from bypass path 377 (here coding the hash accumulated through the prior stage) is selected by filtration MUX 362 and supplied for downstream use in the next stage.

Contents of the fourth indexed position of the bank associated with the third stage also code a hash rule (i.e., hash rule HR7) that, for purposes of illustration, we again assume matches the corresponding field value parsed from the packet header. Accordingly, that matched field value is combined with the output of the prior stage using XOR 373 and supplied to HI logic 343 for use in a hash-intermediate computation, the results of which are passed through filtration MUX 363 based on a select signal appropriate for the matched hash rule.

Because the fourth indexed position of the bank associated with the fourth stage codes a non-hash rule, the last hash rule match (during this fourth and final cycle through the filtered hash chain) is in the third stage and accordingly select signal 514 directs second-level filtration MUX 364 to couple through the corresponding input and supply it as output 559. Output 559 is passed to hash final (HF) logic 252, which in turn supplies hash result 503 encoding the hash contributions accumulated based on four cycles through filtered hash chain and evaluation (by evaluation logic 333) of hash rules {HR0, HR1, HR2, HR3, HR4, HR5, HR6, HR7} against respective field values parsed from a current packet header.

FIGS. 6 and 7 illustrate, in accordance with some embodiments of the present invention, corresponding in-memory footprints for rule sequences that produce a consistent hash despite dissimilar allocations of individual hash rule entries to memory banks. Successive cycles through a 4-stage filtered hash chain with an in-memory allocation of rule entries to banks consistent with FIG. 6 was illustrated and described above with reference to FIGS. 3-5. Based on the description herein, persons of ordinary skill in the art will appreciate that, despite the different allocation of rule entries to banks in FIG. 7, propagation of hash intermediate contributions in successive cycles through the 4-stage filtered hash chain described above results in an identical hash.

Other Embodiments

Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, while techniques have been described in the context of particular communication controller configurations and hashes of packet header field values, the described techniques have broad applicability to other rule evaluation and hash generator designs in which it may be desirable to decouple match rule evaluation order and ordering of contributions to a hash function. Similarly, although the techniques have been described in the context of multi-cycle evaluations through a comparatively 4-stage filtered hash chain, in some embodiments, a longer (or shorted) filtered hash chain may be useful and fewer (or more) cycles such a filtered hash chain may be consistent with design objectives. Indeed, in some embodiments, a hash generator need not even employ a filtered hash chain.

Embodiments of the present invention may be implemented using any of a variety of different hash functions, processing architectures and logic families and may employ hash generation for any of a variety of different purposes, including core-affinity packet traffic routing, load balance, etc. using any appropriate criteria. Accordingly, while FIG. 1 together with its accompanying description relates to an exemplary multiprocessor- or multicore-type information processing architecture in which core-affinity is a design goal, the exemplary architecture is merely illustrative. Of course, architectural descriptions herein have been simplified for purposes of discussion and those skilled in the art will recognize that illustrated boundaries between logic blocks or components are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements and/or impose an alternate decomposition of functionality upon various logic blocks or circuit elements.

Articles, systems and apparati that implement the present invention are, for the most part, composed of electronic components, circuits, rule entries and/or code (e.g., software, firmware and/or microcode) known to those skilled in the art and functionally described herein. Accordingly, component, circuit and code details are explained at a level of detail necessary for clarity, for concreteness and to facilitate an understanding and appreciation of the underlying concepts of the present invention. In some cases, a generalized description of features, structures, components or implementation techniques known in the art is used so as to avoid obfuscation or distraction from the teachings of the present invention.

Finally, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and consistent with the description herein, a broad range of variations, modifications and extensions are envisioned. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims. 

What is claimed is:
 1. An apparatus comprising: a communication controller that, for at least some received information frames, computes a non-commutative hash over an ordered subset of field values from respective headers associated with the received information frames, wherein the communication controller determines a particular ordered subset of field values for inclusion in the non-commutative hash based on execution of match rules that, for respective information frames, evaluate selected ones of the field values in an order that differs from that of the ordered subset of field values over which the non-commutative hash is computed.
 2. The apparatus of claim 1, further comprising: plural processing elements configured to operate on content from respective information frames in accord with protocols layered atop those implemented by the communication controller, the communication controller configured to distribute the content from respective information frames amongst the plural processing elements in accord with the computed non-commutative hashes.
 3. The apparatus of claim 2, wherein the processing elements configured to receive the content distributed thereto together with respective ones of the non-commutative hashes computed at the communications controller; and the processing elements configured to use a particular non-commutative hash received together with particular content as an index to retrieve a context for processing the particular content in connection with one or more of the layered atop protocols.
 4. The apparatus of claim 3, wherein distribution by the communication controller of hypertext transfer protocol data from a particular one of the information frames to a particular one of the processing elements is based on the computed non-commutative hash and is in accord with a load balance criterion; and wherein the retrieval of a processing context particular to the hypertext transfer protocol (HTTP) data from the particular information frame is also based on the computed hash and is in accord with a targeted website context identified, at least in part, using the computed hash as a key therefor.
 5. The apparatus of claim 3, wherein the processing context retrieved based on the particular hash is one of: a web server context HTTP protocol traffic; a cached L2 or L3 lookup table identified for a packet forwarding application; a session initiation protocol (SIP) routing table indexed for particular SIP traffic; and media content indexed for a particular source, wherein the particular hash includes in the hashed over set of field values an addressing field for particular media transfer protocol traffic.
 6. The apparatus of claim 1, wherein for at least a first subset of the received information frames, the communications controller computes respective hashes over a first ordered subset of field values; and wherein for at least a second subset of the received information frames, the communications controller computes respective hashes over a second ordered subset of field values, the first and second subsets of field values being dissimilar in either or both of constituent fields and ordering thereof.
 7. The apparatus of claim 6, wherein the first subset of received information frames includes respective Internet Protocol (IP) packet headers that encode an IP_source_address, an IP_destination_address and a transmission control protocol (TCP) protocol and further include data that identify a hypertext transport protocol (HTTP) associated destination_port, and wherein the first ordered subset of field values over which a respective hash is computed is {IP_source_address, IP_destination_address, protocol, source_port, destination_port}.
 8. The apparatus of claim 6, wherein the second subset of received information frames includes respective Internet Protocol (IP) packet headers that encode an IP_source_address, an IP_destination_address, and a internet message control protocol (ICMP) protocol, and wherein the second ordered subset of field values over which a respective hash is computed is {IP_source_address, IP_destination_address}.
 9. The apparatus of claim 1, wherein the communications controller further includes: storage for field values parsed from the received information frames; evaluation logic that evaluates match rules against respective ones of the parsed field values in accordance with an evaluation order; and hash logic that applies the non-commutative hash based on respective ones of the parsed field values in accordance with a hash order that differs from the evaluation order.
 10. The apparatus of claim 9, wherein the evaluation logic and the hash logic are coupled to receive parsed field values from the storage in accord with the respective evaluation and hash orders.
 11. The apparatus of claim 9, wherein the evaluation logic includes plural elements that evaluate respective match rules in parallel based on field values retrieved from the storage; and wherein the hash logic is configured as a hash chain of plural stages, each stage corresponding to one of the evaluation logic elements and coupled to selectively introduce a successive contribution to the non-commutative hash based on a respective one of the parsed field values and on a match result computed at the corresponding evaluation logic elements.
 12. A method of processing information frames, the method comprising: at a communications controller, evaluating in an evaluation order a first subset of field values parsed from a particular one of plural information frames; based on results of the evaluation, selecting a second subset of the parsed field values and applying a non-commutative hash thereto, wherein the non-commutative hash is applied in a hash order that differs from the evaluation order; for at least a first subset of the information frames, computing the respective non-commutative hashes over a first ordered subset of field values; and for at least a second subset of information frames, computing respective non-commutative hashes over a second ordered subset of field values, the first and second subsets of field values being dissimilar with respect to either or both of constituent fields and ordering thereof.
 13. The method of claim 12, further comprising: storing the parsed field values in storage accessible to both evaluation logic and hash logic of the communications controller.
 14. The method of claim 12, further comprising: parsing the field values from one or more headers associated with the particular information frame.
 15. The method of claim 12, further comprising: distributing content from respective information frames, including the particular information frame, amongst plural processing elements, wherein the distribution is in accord with respective non-commutative hashes applied to respective ordered subsets of field values parsed from the respective information frames.
 16. The method of claim 15, further comprising: at the plural processing elements, operating on content from the respective information frames in accord with protocols layered atop those implemented by the communication controller; and using the respective non-commutative hashes computed at the communications controller as hash keys to retrieve relevant processing contexts in connection with one or more of the layered atop protocols.
 17. A method of processing information frames, the method comprising: at a communications controller, evaluating in a first order a first subset of field values parsed from a first information frame; and based on results of the evaluation, selecting a second subset of the parsed field values and applying a non-commutative hash thereto, wherein the non-commutative hash is applied in a second order that differs from the first order, wherein the non-commutative hash is selected from a set that includes: an ORD-type hash; and a CRC-type hash.
 18. A method of processing information frames, the method comprising: at a communications controller, parsing headers associated with respective information frames and computing respective non-commutative hashes over respective ordered subsets of field values parsed from the respective headers; using the non-commutative hashes to distribute the respective information frames amongst plural processing elements in accordance with a load balance criterion, the processing elements operating on content of the distributed information frames in accord with protocols layered atop those implemented by the communication controller; at each of the plural processing elements, processing respective ones of the information frames distributed thereto; and for at least some of the distributed information frames, using the non-commutative hashes computed at the communications controller and used to distribute the respective information frames as a hash key to retrieve a processing context relevant to a particular execution instance of the respective layered atop protocol.
 19. The method of claim 18, wherein for at least a first subset of the information frames, the respective non-commutative hashes are computed over a first subset of field values, and wherein for at least a second subset of the information frames, the respective hashes are computed over a second subset of field values, the first and second subsets of field values being dissimilar. 